代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
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qmsg compare.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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cfg compxlib.cfg
#*****************************************************************
# compxlib initialization file (compxlib.cfg) *
#
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txt note.txt
*****************************
本程序只供交流学习之用
作者：woailiushui
2006/05/12
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编译环境：quartus2 4.0
语言：Verilog
可直接使用，完成对输入信号的整数，半整数分频
(0.5 和 1 没做 ^_^)
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v port_info_test.v
/**********************************************************************
* $port_info example -- C source code using VPI PLI routines
*
* For the book, "The Verilog PLI Handbook", Chapter 5
* C
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v count_all_prims_test.v
/**********************************************************************
* $count_primitives example -- Verilog HDL test bench.
*
* Verilog test bench to test the $count_primitives PLI applicatio
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v read_delays_test.v
/**********************************************************************
* $list_delays example -- Verilog HDL test bench.
*
* Verilog test bench to test the $list_delays PLI application.
*
*
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v read_attribute_test.v
/**********************************************************************
* $read_attribute example -- Verilog HDL test bench.
*
* Verilog test bench to test the $read_attribute PLI application.
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v show_value_test.v
/**********************************************************************
* $show_value example -- Verilog HDL test bench.
*
* Verilog test bench to test the $show_value PLI application on a
*
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v port_info_test.v
/**********************************************************************
* $port_info example -- Verilog test bench source code
*
* Verilog test bench to test the $port_info PLI application.
*
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v my_monitor_test.v
/**********************************************************************
* $my_monitor example -- Verilog test bench source code
*
* Verilog test bench to test the $my_monitor PLI application on