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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl2_i_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity orcy is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
ci
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufsn is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_f_16 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iobufnsn_s is
port(
o : out vl_logic;
io : inout vl_logic;
i : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cy4_09 is
generic(
cds_action : string := "ignore"
);
port(
c0 : out vl_logic;
c1
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ildi_1u is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup is
generic(
cds_action : string := "ignore"
);
port(
donein : out vl_logic;
q1q4
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lut2 is
generic(
init : integer := 0
);
port(
o : out vl_logic;
i0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos25_f_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i