代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/231894/14216690
html fft_example.html
A.h:hover { color: "#FF0000"; }
A.menu:link { text-decoration: none}
A.menu:visited{ text-decoration: none}
A.menu:hover {color: #EE9B06;}
A.submenu:link { text-decoration: none;}
www.eeworm.com/read/231687/14223291
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity KeypadScan_tb_v_tf is
end KeypadScan_tb_v_tf;
www.eeworm.com/read/231687/14223378
versim_par keypadscan.versim_par
KeypadScan.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/231687/14223383
gfl projnav.gfl
# XST (Creating Lso File) :
KeypadScan.lso
# xst flow : RunXST
KeypadScan.syr
KeypadScan.prj
KeypadScan.sprj
KeypadScan.ana
KeypadScan.stx
KeypadScan.cmd_log
KeypadScan.ngc
KeypadScan.ngr
www.eeworm.com/read/231687/14223415
npl projnav.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT ProjNav
DESIGN projnav
DEVFAM xbr
DEVFAMTIME 0
DEVICE xc2c32a
DEVICETIME 1109962640
DEVPKG CP56
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
www.eeworm.com/read/127506/14351279
versim_xlate fen.versim_xlate
fen.versim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/127506/14351421
versim_map fen.versim_map
fen.versim_map -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/127506/14351426
versim_par fen.versim_par
fen.versim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_Verilog
www.eeworm.com/read/228929/14357593
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity top_tb is
generic(
periode : integer := 25
);
end top_tb;
www.eeworm.com/read/123341/14637162
txt 目录.txt
目 录
译者序
前言
第1章 简介 1
1.1 什么是Verilog HDL？ 1
1.2 历史 1
1.3 主要能力 1
第2章 HDL指南 4
2.1 模块 4
2.2 时延 5
2.3 数据流描述方式 5
2.4 行为描述方式 6
2.5 结构化描述形式 8
2.6 混合设计描述方式 9
2.7 设计模拟