代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/260834/11699270
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sms4_en_ori_test is
end sms4_en_ori_test;
www.eeworm.com/read/260834/11699284
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ck is
port(
ck : out vl_logic_vector(0 to 31);
counter : in vl_logic_vector(0 to 4)
);
end ck;
www.eeworm.com/read/260834/11699311
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sms4_ori_test_01 is
end sms4_ori_test_01;
www.eeworm.com/read/260834/11699329
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sms4_ori_test_00 is
end sms4_ori_test_00;
www.eeworm.com/read/347114/11699398
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and1 is
port(
\Y\ : out vl_logic;
\IN1\ : in vl_logic
);
end and1;
www.eeworm.com/read/347114/11699471
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_asynch_lcell is
generic(
operation_mode : string := "normal";
sum_lutc_input : string := "datac";
lut_mask
www.eeworm.com/read/157036/11744277
log leospec.log
LeonardoSpectrum for Altera - 2005a.82 (Release Production Release, compiled Aug 2 2005 at 02:10:57)
Copyright 1990-2004 Mentor Graphics. All rights reserved.
Portions copyright 1991-2004 Compuwar
www.eeworm.com/read/260117/11746509
jid uart_v.jid
. uart ..\..\..\uart_verilog\uart.v "f:\custmor training\uart_verilog\uart.v"
u2 txmit ..\..\..\uart_verilog\txmit.v "f:\custmor training\uart_verilog\txmit.v"
u1 rcvr ..\..\..\uart_verilog\rcvr.v "
www.eeworm.com/read/259554/11783122
txt 目录.txt
目 录
译者序
前言
第1章 简介 1
1.1 什么是Verilog HDL？ 1
1.2 历史 1
1.3 主要能力 1
第2章 HDL指南 4
2.1 模块 4
2.2 时延 5
2.3 数据流描述方式 5
2.4 行为描述方式 6
2.5 结构化描述形式 8
2.6 混合设计描述方式 9
2.7 设计模拟 10
第3章 Veril
www.eeworm.com/read/345339/11819119
smsg da_tlc5620.map.smsg
Warning (10268): Verilog HDL information at dac_test.v(87): Always Construct contains both blocking and non-blocking assignments