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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb4_s1 is
generic(
cds_action : string := "ignore";
init_00 : integer := 0;
init_01 : integer := 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fdse_1 is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult_and is
generic(
cds_action : string := "ignore"
);
port(
lo : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ofdt_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_s_24 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity startup_spartan2 is
generic(
cds_action : string := "ignore"
);
port(
clk : in vl_logic;
gsr
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity osc4 is
generic(
cds_action : string := "ignore";
period : integer := 100
);
port(
f8m
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos18_s_2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvcmos15_f_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obufd_f is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i