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Verilog 的代码
verilog.v
// generated by newgenasym Tue Nov 04 09:31:32 2008
module res4s (a, b);
parameter size = 1;
inout [size-1:0] a;
inout [size-1:0] b;
initial
begin
end
endmodul
verilog.v
// generated by newgenasym Wed Oct 29 14:16:34 2008
module ind (a, b);
inout a;
inout b;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Wed Oct 29 14:15:22 2008
module cappol (n, p);
inout n;
inout p;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Wed Oct 29 14:14:55 2008
module cap (a, b);
inout a;
inout b;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Thu Oct 30 21:46:29 2008
module ltc3713 (bg, boost, fcb, intvcc, ion, ith, pgnd1, pgnd2, pgood, \run/ss ,
\sense+ , \sense- , sgnd1, sgnd2, shdn_n, sw1, sw2, tg,
verilog.v
// generated by newgenasym Thu Oct 23 15:07:18 2008
module tle2037a (m, n1, n2, out, p, vm, vp);
input m;
output n1;
input n2;
output out;
input p;
input vm;
input vp;
verilog.v
// generated by newgenasym Fri Oct 31 19:08:47 2008
module \74lvth240 (a1_1, a1_2, a1_3, a1_4, a2_1, a2_2, a2_3, a2_4, epad, gnd,
oe1_n, oe2_n, vcc, y1_1, y1_2, y1_3, y1_4, y2_1, y2_2, y2_
verilog.v
// generated by newgenasym Wed Oct 22 14:13:23 2008
module tlc5602 (agnd, aout, avdd1, avdd2, clk, comp, d0, d1, d2, d3, d4, d5, d6,
d7, dgnd, dvdd1, dvdd2, ref);
input agnd;
output
verilog.v
// generated by newgenasym Tue Oct 21 18:57:15 2008
module nvregg79x (gnd, in, in1, in2, in3, out);
input gnd;
input in;
input in1;
input in2;
input in3;
output out;
i
verilog.v
// generated by newgenasym Wed Oct 22 12:30:42 2008
module tl081c (m, n1, n2, out, p, vm, vp);
input m;
input n1;
input n2;
output out;
input p;
input vm;
input vp;