verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 18 行

// generated by newgenasym  Tue Oct 21 18:57:15 2008


module nvregg79x (gnd, in, in1, in2, in3, out);
    input gnd;
    input in;
    input in1;
    input in2;
    input in3;
    output out;


    initial
        begin
        end

endmodule