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找到约 19,564 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvttl_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram128x1s_1 is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
o
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gt_aurora_2 is
generic(
chan_bond_mode : string := "OFF";
chan_bond_one_shot: string := "FALSE";
clk_cor_insert_idle_fl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_f_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdx_u is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_flag is
generic(
cds_action : string := "ignore"
);
port(
i : in vl_logic
);
end x_flag;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifd_f is
generic(
cds_action : string := "ignore";
init : integer := 0
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuf_lvcmos15_f_6 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ifdxi is
generic(
cds_action : string := "ignore";
init : integer := 1
);
port(
q :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_sstl2_ii_dci is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i