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Verilog 的代码
verilog.v
// generated by newgenasym Tue Oct 21 18:57:15 2008
module nvregg79x (gnd, in, in1, in2, in3, out);
input gnd;
input in;
input in1;
input in2;
input in3;
output out;
i
verilog.v
// generated by newgenasym Wed Oct 22 12:30:42 2008
module tl081c (m, n1, n2, out, p, vm, vp);
input m;
input n1;
input n2;
output out;
input p;
input vm;
input vp;
verilog.v
// generated by newgenasym Fri Oct 31 17:18:34 2008
module \74lvth373 (d1, d2, d3, d4, d5, d6, d7, d8, gnd, le, oe_n, q1, q2, q3, q4, q5,
q6, q7, q8, vcc);
input d1;
input d2;
verilog.v
// generated by newgenasym Wed Oct 29 23:15:07 2008
module \74lvth245 (a1, a2, a3, a4, a5, a6, a7, a8, b1, b2, b3, b4, b5, b6, b7, b8, dir,
gnd, oe_n, vcc);
input a1;
input a2;
verilog.v
// generated by newgenasym Tue Nov 04 09:34:15 2008
module timer (cont, disch, gnd, out, reset, thres, trig, vcc);
input cont;
input disch;
input gnd;
output out;
input reset;
verilog.v
// generated by newgenasym Wed Oct 29 23:13:05 2008
module ltc4242c (auxfault1_n, auxfault2_n, auxin1, auxin2, auxon1, auxon2,
auxout1, auxout2, auxpgood1_n, auxpgood2_n, en1_n, en2_n,
verilog.v
// generated by newgenasym Tue Nov 04 09:34:48 2008
module \74lvth125 (a1, a2, a3, a4, gnd, oe1_n, oe2_n, oe3_n, oe4_n, vcc, y1, y2, y3,
y4);
input a1;
input a2;
input a3;
verilog.v
// generated by newgenasym Tue Oct 21 18:34:25 2008
module lm317 (adj, in, out);
input adj;
input in;
input out;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Wed Oct 29 23:14:11 2008
module \74lvth244 (\1a1 , \1a2 , \1a3 , \1a4 , \1oe_n , \1y1 , \1y2 , \1y3 , \1y4 , \2a1 , \2a2 , \2a3 ,
\2a4 , \2oe_n , \2y1 , \2y2 , \
verilog.v
// generated by newgenasym Tue Nov 04 14:14:39 2008
module mpc8641d (agnd_srds1, agnd_srds2, asleep, avdd_core0, avdd_core1,
avdd_lb, avdd_plat, avdd_srds1, avdd_srds2, \ckstp_in* ,