代码搜索：Vector
找到约 10,000 项符合「Vector」的源代码
代码结果 10,000
www.eeworm.com/read/267307/6933119
vhd edge.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity EDGE is
port (
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
VOLTAGE_TRI : IN std_logic_vector (7 downto 0);
TRIGGER : OUT STD_LOGIC
)
www.eeworm.com/read/267307/6933418
vhd edge.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity EDGE is
port (
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
VOLTAGE_TRI : IN std_logic_vector (7 downto 0);
TRIGGER : OUT STD_LOGIC
)
www.eeworm.com/read/251931/6956502
m ip_fft128_model.m
% function [y, exp_out] = ip_fft128_model(x,N,INVERSE)
%
% calculates the complex block-floating p
www.eeworm.com/read/444459/7109208
txt romo_vhd.txt
--------------------------------------------------------------------------------
-- --
-- V H D L
www.eeworm.com/read/279662/7110781
cpp vectoradd.cpp
#include
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_cpu( float* a, float* b, float *c, int size )
{
for( int i = 0; i < size; ++ i )
www.eeworm.com/read/461652/7222752
vhd output.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/459461/7275182
vhd yuv.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity yuv is port(
y1,u,v,y2: in std_logic_vector(7 downto 0);
r1,g1,b1: out std_logic_
www.eeworm.com/read/457410/7325877
vhd aes_tester.vhd
--*************************************************************************
-- Project : AES128 *
--
www.eeworm.com/read/198871/7905381
c storage.c
/***********************************************************************
*
* Handle storage allocation and deallocation for multi-dimensional
* arrays.
*
* Allocation routines return NULL o
www.eeworm.com/read/298886/7927516
vhd yuv.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity yuv is port(
y1,u,v,y2: in std_logic_vector(7 downto 0);
r1,g1,b1: out std_logic_