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V1 4 FL f:/lqj/1/bulkin/fpga/top.vhdl 2006/10/24.11:23:48 FL F:/lqj/1/BulkOut/FPGA/top.vhdl 2006/11/13.11:10:28 EN work/TOP FL F:/lqj/1/BulkOut/FPGA/top.vhdl PB ieee/STD_LOGIC_1164 \

-- Xilinx Vhdl produced by program ngd2vhdl F.26 -- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log i2c.nga i2c_timesim.vhd -- Input file: i2c.nga -- Output file: i2c_timesim

-- mc8051.vhd -- -- This file is a part of the UMR MC8051 VHDL model -- Copyright (C) 2001 University of Missouri-Rolla (UMR) -- -- The UMR MC8051 VHDL model is free software; you can redistribute

-- E:\VHDL\TIMER\KEYDETC_TB.VHD -- VHDL Test Bench created by -- Visual Software Solution's HDL Bencher 1.02 -- Product info/updates: www.testbench.com -- Support: support@testbench.com -- Sales:

-- mul32c.vhdl parallel multiply 32 bit x 32 bit to get 64 bit unsigned product -- uses add32 component and fadd component, includes carry save -- uses VHDL 'generate' to hav

compxlib.log: compxlib Program Version 6.3i, Xilinx Inc Source Tools => [using user specified simulator path (-p) value] output directory :- (vhdl) : D:\Xilinx\vhdl\mti_se checking dep

compxlib.log: compxlib Program Version 6.3i, Xilinx Inc Source Tools => [using user specified simulator path (-p) value] output directory :- (vhdl) : D:\Xilinx\vhdl\mti_se checking dep

-- mul32c.vhdl parallel multiply 32 bit x 32 bit to get 64 bit unsigned product -- uses add32 component and fadd component, includes carry save -- uses VHDL 'generate' to hav

-- E:\VHDL\TIMER\KEYDETC_TB.VHD -- VHDL Test Bench created by -- Visual Software Solution's HDL Bencher 1.02 -- Product info/updates: www.testbench.com -- Support: support@testbench.com -- Sales:

-- E:\VHDL\TIMER\KEYDETC_TB.VHD -- VHDL Test Bench created by -- Visual Software Solution's HDL Bencher 1.02 -- Product info/updates: www.testbench.com -- Support: support@testbench.com -- Sales: