keydetc_tb.vhd

这是关于VHDL时钟的源代码

-- E:\VHDL\TIMER\KEYDETC_TB.VHD
-- VHDL Test Bench created by
-- Visual Software Solution's HDL Bencher 1.02
-- Product info/updates: www.testbench.com
-- Support: [e-mail]
-- Sales: [e-mail] / call [phone]
-- Wed Jun 06 09:20:31 2001

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 93
FILE RESULTS: TEXT IS OUT "results.txt";
	COMPONENT keydetc
		PORT (
			clk_5ms : in  std_logic;
			clk_1us : in  std_logic;
			adj : in  std_logic;
			up : in  std_logic;
			mode : out  std_logic_vector (3 DOWNTO 0);
			inc : out  std_logic
		);
	END COMPONENT;

	SIGNAL clk_5ms : std_logic;
	SIGNAL clk_1us : std_logic;
	SIGNAL adj : std_logic;
	SIGNAL up : std_logic;
	SIGNAL mode : std_logic_vector (3 DOWNTO 0);
	SIGNAL inc : std_logic;

BEGIN
	UUT : keydetc
	PORT MAP (
		clk_5ms => clk_5ms,
		clk_1us => clk_1us,
		adj => adj,
		up => up,
		mode => mode,
		inc => inc
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_mode(
			next_mode : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (mode /= next_mode) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns mode="));
				write(TX_LOC, mode);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_mode);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_inc(
			next_inc : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 512);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (inc /= next_inc) THEN 
				write(TX_LOC,string'("Error at time="));
				write(TX_LOC, TX_TIME);
				write(TX_LOC,string'("ns inc="));
				write(TX_LOC, inc);
				write(TX_LOC, string'(", Expected = "));
				write(TX_LOC, next_inc);
				write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				writeline(results, TX_LOC);
				Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		clk_5ms <= transport '0';
		clk_1us <= transport '0';
		adj <= transport '0';
		up <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=3 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=6 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=23 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=40 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=43 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=46 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=63 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=80 ns
		clk_1us <= transport '0';
		adj <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=83 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=86 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=103 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=120 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=123 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=126 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=143 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=160 ns
		clk_1us <= transport '0';
		up <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=163 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=166 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=183 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=200 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=203 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=206 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=223 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=240 ns
		clk_1us <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=243 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=246 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=263 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=280 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=283 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=286 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=303 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=320 ns
		clk_1us <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=323 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=326 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=343 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=360 ns
		clk_1us <= transport '1';
		adj <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=363 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=366 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=383 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=400 ns
		clk_1us <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=403 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=406 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=423 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=440 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=443 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=446 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=463 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=480 ns
		clk_1us <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=483 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=486 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=503 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=520 ns
		clk_1us <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=523 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=526 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=543 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=560 ns
		clk_1us <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=563 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=566 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=583 ns
		clk_5ms <= transport '0';
		-- --------------------
		WAIT FOR 17 ns; -- Time=600 ns
		clk_1us <= transport '1';
		adj <= transport '1';
		up <= transport '0';
		-- --------------------
		WAIT FOR 3 ns; -- Time=603 ns
		clk_5ms <= transport '1';
		-- --------------------
		WAIT FOR 3 ns; -- Time=606 ns
		-- --------------------
		WAIT FOR 17 ns; -- Time=623 ns