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anal.out
Loading db file 'D:/Synopsys/FPGA_Express/lib/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd:
anal.out
Loading db file 'D:/Synopsys/FPGA_Express/lib/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd:
test.vhd
-- Project: VHDL to Verilog RTL translation
-- Revision: 1.0
-- Date of last Revision: February 27 2001
-- Designer: Vincenzo Liguori
-- vhd2vl test file
-- This VHDL fil
LIBRARY IEEE;
USE IEEE.
image.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
coregen.log
# Xilinx CORE Generator 6.3i
# User = administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_
st2fsm.vhd
------------------------------------------------------------------------------------------
--[Disclaimer]
--This VHDL code and all associated documentation, comments or other information
--(co
bin2gray.vhd
-------------------------------------------------------------------------------
-- Title : Binary-to-Gray converter
-- Project : VHDL Library of Arithmetic Units
----------------------------
dec.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix decrementer
-- Project : VHDL Library of Arithmetic Units
-------------------------
gray2bin.vhd
-------------------------------------------------------------------------------
-- Title : Gray-to-binary converter
-- Project : VHDL Library of Arithmetic Units
----------------------------
addmuluns.vhd
-------------------------------------------------------------------------------
-- Title : Unsigned adder-multiplier
-- Project : VHDL Library of Arithmetic Units
---------------------------