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VHDL 的代码
compvhdl.do
# Rev: 2.1 24Jan05 TFB - Production
# setup language: vhdl or verilog
quietly set LANG "vhdl"
#quietly set LANG "vlog"
if { $LANG == "vlog" } {
quietly set LANGDIR "verilog"
} else {
qu
compvlog.do
# Rev: 2.1 24Jan05 TFB - Production
# setup language: vhdl or verilog
#quietly set LANG "vhdl"
quietly set LANG "vlog"
if { $LANG == "vlog" } {
quietly set LANGDIR "verilog"
} else {
qu
compvhdl.do
# Rev: 2.1 24Jan05 TFB - Production
# setup language: vhdl or verilog
quietly set LANG "vhdl"
#quietly set LANG "vlog"
if { $LANG == "vlog" } {
quietly set LANGDIR "verilog"
} else {
qu
compvlog.do
# Rev: 2.1 24Jan05 TFB - Production
# setup language: vhdl or verilog
#quietly set LANG "vhdl"
quietly set LANG "vlog"
if { $LANG == "vlog" } {
quietly set LANGDIR "verilog"
} else {
qu
compvhdl.do
# Rev: 2.1 24Jan05 TFB - Production
# setup language: vhdl or verilog
quietly set LANG "vhdl"
#quietly set LANG "vlog"
if { $LANG == "vlog" } {
quietly set LANGDIR "verilog"
} else {
qu
测试向量（test bench）和波形产生：vhdl实例---波形发生器（含test beach）.txt
-----------------------------------------------------------------------------
--
-- The following information has been generated by Exemplar Logic
-- and may be freely distributed and mod
测试向量（test bench）和波形产生：vhdl实例---波形发生器（含test beach）.txt
-----------------------------------------------------------------------------
--
-- The following information has been generated by Exemplar Logic
-- and may be freely distributed and mod