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AVR_Core/VHDL
uart_struct.vhd
-------------------------------------------------------------------------------
-- --
-- VHDL UART IP core
uut_tx_wrapper.prj
vhdl work "DDR_6TO1_16CHAN_RT_TX.vhd"
vhdl work "uut_tx_wrapper.vhd"
testmem.gfl
# VHDL : PDCL (jhdparse)
__projnav/testmem_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/testmem_jhdparse_tcl.rsp
dcm_0_wrapper_xst.prj
VHDL dcm_module_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a/hdl/vhdl/dcm_module.vhd
vhdl work ../hdl/dcm_0_wrapper.vhd
dcm_0_wrapper_xst.prj
VHDL dcm_module_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a/hdl/vhdl/dcm_module.vhd
vhdl work ../hdl/dcm_0_wrapper.vhd
rs232_uart_1_wrapper_xst.prj
VHDL common_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\common_v1_00_a/hdl/vhdl/pselect.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vh
rs232_uart_1_wrapper_xst.prj
VHDL common_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\common_v1_00_a/hdl/vhdl/pselect.vhd
VHDL opb_uartlite_v1_00_b g:\EDK\hw\XilinxProcessorIPLib\pcores\opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vh
hdpdeps.ref
V1 109
FL E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl 2007/03/16.20:38:38
FL e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl 2007/03/16.20:47:20
FL E:/qiangdaqi4ren/fpq1s.vhdl 2007/03/16.21:15:22
FL E:/VHD
hdpdeps.ref
V1 109
FL E:/VHDL/wait316/qiangdaqi4ren/ymq.vhdl 2007/03/16.20:38:38
FL e:/vhdl/test_12jiao/qiangdaqi4ren/feng.vhdl 2007/03/16.20:47:20
FL E:/qiangdaqi4ren/fpq1s.vhdl 2007/03/16.21:15:22
FL E:/VHD