uart_struct.vhd

Run Pac-man Game Based on 8086/8088 FPGA IP Core

-------------------------------------------------------------------------------
--                                                                           --
--  VHDL UART IP core                                             --
--  Copyright (C) 2005 HT-LAB                                                --
--                                                                           --
--  Contact : mailto:[e-mail]                                        --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Architecture UART.uart.symbol
--
-- Created: by - Hans 21/07/2005
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY uart IS
   GENERIC( 
      DIVIDER : integer := 7
   );
   PORT( 
      abus    : IN     std_logic_vector (1 DOWNTO 0);
      clk     : IN     std_logic;
      csn     : IN     std_logic;
      dbusin  : IN     std_logic_vector (7 DOWNTO 0);
      rdn     : IN     std_logic;
      resetn  : IN     std_logic;
      rx      : IN     std_logic;
      wrn     : IN     std_logic;
      dbusout : OUT    std_logic_vector (7 DOWNTO 0);
      tx      : OUT    std_logic
   );

-- Declarations

END uart ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

ARCHITECTURE struct OF uart IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL dbusrx   : std_logic_vector(7 DOWNTO 0);
   SIGNAL ferror   : std_logic;
   SIGNAL rdn_s    : std_logic;
   SIGNAL rdrf     : std_logic;
   SIGNAL rxenable : std_logic;
   SIGNAL tdre     : std_logic;
   SIGNAL txenable : std_logic;
   SIGNAL wrn_s    : std_logic;


signal divtx_s : std_logic_vector(3 downto 0);
signal divreg_s : std_logic_vector(7 downto 0);
signal divcnt_s : std_logic_vector(7 downto 0);
signal rxclk16_s : std_logic;

   -- Component Declarations
   COMPONENT uartrx
   PORT (
      clk    : IN     std_logic ;
      enable : IN     std_logic ;                  -- 16 x bit_rate receive clock enable
      resetn : IN     std_logic ;
      dbus   : OUT    std_logic_vector (7 DOWNTO 0);
      rdn    : IN     std_logic ;
      rdrf   : OUT    std_logic ;
      ferror : OUT    std_logic ;
      rx     : IN     std_logic 
   );
   END COMPONENT;
   COMPONENT uarttx
   PORT (
      clk    : IN     std_logic ;
      enable : IN     std_logic ;                    -- 1 x bit_rate Transmit clock enable
      resetn : IN     std_logic ;
      dbus   : IN     std_logic_vector (7 DOWNTO 0); -- input TO txshift register
      tdre   : OUT    std_logic ;
      wrn    : IN     std_logic ;
      tx     : OUT    std_logic 
   );
   END COMPONENT;


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   -- eb1 1                     
                      
   -- COM1, 0x3F8-0x3FF, Int 0C, Vector 30-33
   -- COM2, 0x2F8-0x2FF, Int 0B, Vector 2C-2F
   -- 03F8 -> address=0 Read/Write Data
   -- 03F9 -> address=1 Status
   -- 03FA -> address=2 Divider 
   
   -------------------------------------------------------------------------------
   -- Chip Select COM1, active low!
   ------------------------------------------------------------------------------- 
   rdn_s <= '0' when (rdn='0' and csn='0' and (abus="00")) else '1';    -- Read strobe
   wrn_s <= '0' when (wrn='0' and csn='0' and (abus="00")) else '1';    -- Write strobe
   
   process (abus,dbusrx,ferror,tdre,rdrf,divreg_s) 
      begin
        case abus is
          when "00"   => dbusout <= dbusrx;                             -- 0x03F8 Read UART Receive Reg                   
          when "01"   => dbusout <= "00000" & ferror & tdre & rdrf;     -- 0x03F9 Read UART status Reg  
          when others => dbusout <= divreg_s;       
        end case;
   end process;
   
   -------------------------------------------------------------------------------
   -- Bitrate divider, 0x03FA
   -------------------------------------------------------------------------------
     Process (clk,resetn)  
       begin
         if (resetn='0') then                     
            divreg_s <= CONV_STD_LOGIC_VECTOR(DIVIDER,8);                                       
         elsif (rising_edge(clk)) then          
            if wrn='0' and csn='0' and abus="10" then 
                divreg_s <= dbusin;                     
            end if;         
         end if;   
     end process;    
     
   ------------------------------------------------------------------------------
   -- 8 bits divider
   -- Generate rxenable clock (x16)
   ------------------------------------------------------------------------------
   process (clk,resetn)                            -- First divider
      begin
          if (resetn='0') then                     
             divcnt_s <= (others => '0');   
             rxclk16_s <= '0';                     -- Receive clock (x16, pulse)               
          elsif (rising_edge(clk)) then 
            if divcnt_s=divreg_s then
               divcnt_s <= (others => '0');    
               rxclk16_s <= '1';       
            else                                  
               rxclk16_s <= '0';
               divcnt_s <= divcnt_s + '1';  
            end if;
          end if;   
   end process;
   
   rxenable <= rxclk16_s;
   
   ------------------------------------------------------------------------------
   -- divider by 16 
   -- rxclk16/16=txclk
   ------------------------------------------------------------------------------
   process (clk,resetn)                             
      begin
           if (resetn='0') then                     
              divtx_s <= (others => '0');  
              txenable <= '0'; 
           elsif (rising_edge(clk)) then 
              if rxclk16_s='1' then
                  divtx_s <= divtx_s + '1';
               if divtx_s="0000" then
                 txenable <= '1';
               end if;   
            else 
                  txenable <= '0';
            end if;   
           end if;   
   end process;

   -- Instance port mappings.
   I0 : uartrx
      PORT MAP (
         clk    => clk,
         enable => rxenable,
         resetn => resetn,
         dbus   => dbusrx,
         rdn    => rdn_s,
         rdrf   => rdrf,
         ferror => ferror,
         rx     => rx
      );
   I1 : uarttx
      PORT MAP (
         clk    => clk,
         enable => txenable,
         resetn => resetn,
         dbus   => dbusin,
         tdre   => tdre,
         wrn    => wrn_s,
         tx     => tx
      );

END struct;