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synth_lab.gfl
# VHDL : PDCL (jhdparse)
__projnav/data_control_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/mac_ch_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/data_control_fsm_jhdparse_tcl.rsp
#
synth_lab.gfl
# VHDL : PDCL (jhdparse)
__projnav/data_control_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/mac_ch_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/data_control_fsm_jhdparse_tcl.rsp
#
xconfig.in
mainmenu_name "CORE Configuration"
source syn/config.in
source vhdl/core/config.in
source vhdl/bus/config.in
mainmenu_option next_comment
comment 'Peripherals '
source vhdl/peripherals/me
xconfig.in
mainmenu_name "CORE Configuration"
source syn/config.in
source vhdl/core/config.in
source vhdl/bus/config.in
mainmenu_option next_comment
comment 'Peripherals '
source vhdl/peripherals/me
xconfig.in
mainmenu_name "CORE Configuration"
source syn/config.in
source vhdl/core/config.in
source vhdl/bus/config.in
mainmenu_option next_comment
comment 'Peripherals '
source vhdl/peripherals/me
xconfig.in
mainmenu_name "CORE Configuration"
source syn/config.in
source vhdl/core/config.in
source vhdl/bus/config.in
mainmenu_option next_comment
comment 'Peripherals '
source vhdl/peripherals/me
xconfig.in
mainmenu_name "CORE Configuration"
source syn/config.in
source vhdl/core/config.in
source vhdl/bus/config.in
mainmenu_option next_comment
comment 'Peripherals '
source vhdl/peripherals/me
uart_struct.vhd
-------------------------------------------------------------------------------
-- --
-- VHDL UART IP core
i80386.vhd
------------------------------------------------------------------------------
-- --
-- Intel 80386 VHDL model
uart_struct.vhd
-------------------------------------------------------------------------------
-- --
-- VHDL UART IP core