📄 i80386.vhd
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-------------------------------------------------------------------------------- ---- Intel 80386 VHDL model ---- Copyright (C) Convergent, Inc. 1988 ---- ---- File: i80386.vhd ---- Revision: E0.1 ---- Date Created: 6-12-1988 ---- Author: Mark Dakur ---- Function: This VHDL model emulates the Intel 80386 32-bit CPU ---- to the instruction and bus timing level. ---- Generics: Debug 1=Enable Reporting of Model Status. ---- 0=None (Default) ---- Inst ---- Performance ---- Speed ---- Target Simulator: ViewSim ---- ---- Reference Material: Intel Data Book, 80386-20, Oct., 1987 ---- Intel 80386 Programmers Reference, 1986 ---- 80386 Technical Reference, Edmund Strauss, 1987 ---- ---- Verification: No ---- Validation: No ---- Certification: No ---- ---- Behavioral models have two main parts: a package declaration and its ---- corresponding package body, and an entity declaration and its ---- corresponding architecture body. The package declaration and ---- package body define subprograms used by the behavioral model; ---- the entity declaration and architecture body define the behavior ---- of the model. ---- This file contains the entity declaration and architecture. -- -------------------------------------------------------------------------------------------------------------------------------------------------------------- Specification ---- ---- 1.0 Introduction ---- 2.0 Description ---- ---- The i80386 consists of 6 functional units defined as follows: ---- ---- 1) Bus Interface Unit {BIunit} ---- Accepts internal requests for code fetches from the CPunit and -- -- data transfers from the Eunit and prioritizes the requests. ---- It is the interface to the external pins (ports) of the package. ---- ---- 2) Code Prefetch Unit {CPunit} ---- Performs the program look ahead function. When the BIunit is not ---- performing bus cycles to execute an instruction, it uses the BIunit ---- to to fetch sequentially along the instruction byte stream. These ---- prefetched instructions are stored in the 16-byte Code Queue to ---- await processing by the IDunit. ---- ---- 3) Instruction Decode Unit {IDunit} ---- a) Instructions Supported: ---- 1) nop ---- 2) mov eax,"immediate 32 bit data" ---- 3) mov ebx,"immediate 32 bit data" ---- 4) mov eax,[ebx] ---- 5) mov [ebx],eax ---- 6) in al,"byte address" ---- 7) out "byte address",al ---- 8) inc eax ---- 9) inc ebx ---- 10) jmp "label" (relative nears and shorts) ---- ---- 4) Execution Unit {Eunit} ---- a) Control Unit {Cunit} ---- b) Data Unit {Dunit} ---- c) Protection Test Unit {PTunit} ---- ---- 5) Segmentation Unit {Sunit} ---- ---- 6) Paging Unit {Punit} ---- a) Page Translator Unit {PTunit} ---- i) Translation Lookaside Buffer {TLB} ---- a) Page Directory ---- b) Page Table -- -------------------------------------------------------------------------------------------------------------------------------------------------------------- Revision History ---- ---- Revision ---- Level Date Engineer Description ---- -------- ------- --------------- --------------------------------------- ---- E0.1 6-12-88 Dakur First Release -- ---------------------------------------------------------------------------------------------------------------------------------------------------------------- Entity declaration for i80386:---- The following entity declaration begins the definition of the-- behavioral model of the i80386. It declares the model's name-- and its IO signals, or ports. This declaration defines the-- model's interface with enclosing designs; it defines the part-- of the model that is externally visible. Following this-- entity declaration is its corresponding architecture body;-- the architecture body defines the behavior of the model.-------------------------------------------------------------------------PACKAGE i80386 isFUNCTION tohex (CONSTANT value, Bytes: IN INTEGER) RETURN integer;END i80386;PACKAGE BODY i80386 isFUNCTION tohex (CONSTANT value, Bytes: IN INTEGER) RETURN integer IS VARIABLE dWord: vlbit_1d(31 downto 0); VARIABLE Byte: vlbit_1d(31 downto 0); VARIABLE Count: INTEGER;BEGIN Count := 1; dWord := vlbit_vector(value); Convert: WHILE Count <= Bytes LOOP CASE integer(Bytes) is WHEN 4 => CASE Count is WHEN 1 => Byte := X"000000" & dWord(31 downto 24); WHEN 2 => Byte := X"000000" & dWord(23 downto 16); WHEN 3 => Byte := X"000000" & dWord(15 downto 8); WHEN 4 => Byte := X"000000" & dWord(7 downto 0); WHEN OTHERS => NULL; END CASE; WHEN 2 => CASE Count is WHEN 1 => Byte := X"000000" & dWord(15 downto 8); WHEN 2 => Byte := X"000000" & dWord(7 downto 0); WHEN OTHERS => NULL; END CASE; WHEN 1 => Byte := X"000000" & dWord(7 downto 0); WHEN OTHERS => NULL; END CASE; Count := Count + 1; CASE integer(Byte(7 downto 4)) is WHEN 15 => put("F"); WHEN 14 => put("E"); WHEN 13 => put("D"); WHEN 12 => put("C"); WHEN 11 => put("B"); WHEN 10 => put("A"); WHEN 9 => put("9"); WHEN 8 => put("8"); WHEN 7 => put("7"); WHEN 6 => put("6"); WHEN 5 => put("5"); WHEN 4 => put("4"); WHEN 3 => put("3"); WHEN 2 => put("2"); WHEN 1 => put("1"); WHEN 0 => put("0"); WHEN OTHERS => put("X"); END CASE; CASE integer(Byte(3 downto 0)) is WHEN 15 => put("F"); WHEN 14 => put("E"); WHEN 13 => put("D"); WHEN 12 => put("C"); WHEN 11 => put("B"); WHEN 10 => put("A"); WHEN 9 => put("9"); WHEN 8 => put("8"); WHEN 7 => put("7"); WHEN 6 => put("6"); WHEN 5 => put("5"); WHEN 4 => put("4"); WHEN 3 => put("3"); WHEN 2 => put("2"); WHEN 1 => put("1"); WHEN 0 => put("0"); WHEN OTHERS => put("X"); END CASE; END LOOP Convert; put("h"); RETURN 1;END tohex;END i80386;USE work.i80386.tohex;entity i80386 is GENERIC (CONSTANT Debug: BOOLEAN := FALSE; CONSTANT Inst: BOOLEAN := FALSE; CONSTANT Performance: INTEGER := 1; CONSTANT Speed: INTEGER := 32);-- USE: Pass a value to the above generics from attributes attached to the 80386 symbol-- on the schematic.-- Description: Debug; A value of integer 1 (one) means that the model will output-- status information as simulation progresses. The default if no attribute exists is-- FALSE, or no status reported.-- Inst; A value of interger 1 (one) means that the model will output-- instructions. The Debug generic overides this one.-- Performance; 0=min, 1=typ, 2=max-- Speed; Processor speed choices, values are: 0=16MHz, 1=20MHz, 2=25MHZ, 3=30MHz port (BE_n: out vlbit_1d(3 downto 0) := B"0000"; Address: out vlbit_1d(31 downto 2) := B"111111111111111111111111111111"; W_R_n: out vlbit := '0'; D_C_n: out vlbit := '1'; M_IO_n: out vlbit := '0'; LOCK_n, ADS_n: out vlbit := '1'; HLDA: out vlbit := '0'; Data: inout vlbit_1d(31 downto 0) := X"ZZZZZZZZ"; CLK2: in vlbit := '0'; NA_n, BS16_n: in vlbit := '1'; READY_n, HOLD, PERQ: in vlbit := '0'; BUSY_n, ERROR_n: in vlbit := '1'; INTR: in vlbit := '0'; NMI, RESET: in vlbit := '0');-- THE ORDER OF THE PORTS IS IMPORTANT FOR COMPATIBILITY WITH THE "PINORDER"-- ATTRIBUTE ON THE SYMBOL FOR THIS MODEL.end i80386; -------------------------------------------------------------------------------------------------------------------------------------------------- Architecture Body of i80386:---- The following architecture body defines the behavior of the i80386-- model. It consists of a set of process statements and other-- concurrent statements. These statements are all invoked when-- simulation begins, and continue to execute concurrently throughout-- simulation. The statements communicate via the internal signals-- declared at the top of the architecture body. Each statement either-- checks the validity of input signals, or modifies the values of-- output signals or internal signals in response to changes on input-- signals or internal signals.-------------------------------------------------------------------------architecture behavior of i80386 is-- Internal Signals-- These information paths allow for communication between Concurent-- Process Blocks within the model. All signals that are defined here have-- global visibility. Signals, variables and constants defined within process-- blocks have local visibility within that process ONLY. SIGNAL CLK: vlbit := '1'; -- 80386 internal clock=CLK2 / 2 SIGNAL StateNA: vlbit := '1'; SIGNAL StateBS16: vlbit := '1'; SIGNAL RequestPending: vlbit := '1'; CONSTANT Pending: vlbit := '1'; CONSTANT NotPending: vlbit := '0'; SIGNAL NonAligned: vlbit := '0'; SIGNAL ReadRequest: vlbit := '1'; SIGNAL MemoryFetch: vlbit := '1'; SIGNAL CodeFetch: vlbit := '1'; SIGNAL ByteEnable: vlbit_1d(3 downto 0) := X"0"; SIGNAL DataWidth: vlbit_1d(31 downto 0) := X"00000002"; CONSTANT WidthByte: INTEGER := 0; -- Byte CONSTANT WidthWord: INTEGER := 1; -- Word (2 bytes) CONSTANT WidthDword: INTEGER := 2; -- Dword (4 bytes) SIGNAL dWord: vlbit_1d(31 downto 0) := X"00000000"; SIGNAL State: vlbit_1d(31 downto 0) := X"00000000"; -- State Register, Initialized to StateTi CONSTANT StateTi: INTEGER := 0; -- Reset State CONSTANT StateT1: INTEGER := 1; -- First state of a non-pipelined bus cycle⌨️ 快捷键说明
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