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config dummy_root_design; design newpro001_lib.dummy_root_design:sch_1; liblist newpro001_lib, new_library; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl

config dummy_root_design; design newpro001_lib.dummy_root_design:sch_1; liblist newpro001_lib, new_library; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl

config data; design project1_lib.data:sim_sch_1; liblist project1_lib, standard, classlib; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch,

config daamp; design project1_lib.daamp:sim_sch_1; liblist project1_lib, standard, classlib; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arc

config root; design project1_lib.root:sim_sch_1; liblist project1_lib, standard, classlib; viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch,

------------------------------------------------------------------------------- -- Filename: ac97_if_pkg.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ----------------------

------------------------------------------------------------------------------- -- Filename: ac97_if_pkg.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ----------------------

vhdl testbench online course: http://quirk.ece.fcu.edu.tw/~dgliu/vhdl/VHDL-07-01.html -------------------------------------------------------------------------------- uart-project complie order:(

../../design_src/vhdl/rtl/child1.vhd ../../design_src/vhdl/rtl/child2.vhd ../../design_src/vhdl/rtl/child3.vhd ../../design_src/vhdl/rtl/master.vhd ../../design_src/vhdl/src/pred_fns.vhd ../../design_

vhdl work "baud_gen.vhd" vhdl work "baud_gen_test.vhd"