notice.txt

uart_061109.rar

vhdl testbench online course:
http://quirk.ece.fcu.edu.tw/~dgliu/vhdl/VHDL-07-01.html
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uart-project complie order:(if cannot compiled correctly,try this order pls)
amba  device  target  config  sparcv8  mmuconfig  iface   macore  uart  tb_uart
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begin and reset simuli:
signal clk: std_logic := '0';
signal rst: std_logic;
        
begin       
rst <= '0', '1' after 10 ns, '0' after 30 ns;
clk <= not clk after 8 ns;
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UART data register(addr:0x80000070):
the DATA is put in the lowest 8_bits(7 downto 0)

UART control register(addr:0x80000078):           
00000000000000000000000 001110011

UART status register(addr:0x80000074):(read the status of uart)
0000000000000000000000000 

UART scaler register(addr:0x8000007c):(12_bits)
scaler reload value is the lowest 12_bits(11 downto 0).