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内容简介.txt
本书按层次结构论述数字系统，把传统的数字系统与现代技术相结合，深入浅出，详略得当。内容涉及数制，编码，布尔代数，逻辑门，组合逻辑，时序电路，VHDL基本概念，VLSI设计基本概念，COMS逻辑电路和硅芯片，存储器部件，计算机原理和计算机系统结构基础知识。
washer.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
digclk.lfp
# begin LFP file F:\FPGA\VHDL\waitpast\dig_clk_lcd\digclk.lfp
designfile digclk.vhd
parttype xc3s400-5-pq208
bus_delimiter -1;
set_busdelim_onsave 0;
i2c_syplify.prj
#-- Synplicity, Inc.
#-- Version 7.1
#-- Project file D:\My_Design\I2C\synplify\I2C_syplify.prj
#-- Written on Mon Jul 26 11:31:30 2004
#add_file options
add_file -vhdl -lib work "D:/
plj.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
add_files.tcl
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/Cordic/hdl/shiftn_synthesis.vhd}
add_input_file -format {VHDL} -work Cordic {D:/DEMO/demo_hdl_designer/Cordic/hdl/addsub_synthesi
keylock.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
songer.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
alarm.vhd
----vhdl报警设计 ：
---smoke,door,water输入
---en输入允许，alarm_en报警允许 ( L)
---fire_alarm,burg_alarm,water_alarm输出（
alarm.vhd
----vhdl报警设计 ：
---smoke,door,water输入
---en输入允许，alarm_en报警允许 ( L)
---fire_alarm,burg_alarm,water_alarm输出（