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VHDL 的代码
video.csf.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
video.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
__projnav.log
ISE Auto-Make Log File
-----------------------
Updating: Simulate Post-Fit VHDL Model
Starting: 'exewrap -tapkeep -mode pipe -command xilperl __checkModelSim.pl'
Starting: 'xilperl __checkM
core_fft64_flist.txt
# Output products list for
core_fft64.asy
core_fft64.ngc
core_fft64.sym
core_fft64.v
core_fft64.veo
core_fft64.vhd
core_fft64.vho
core_fft64.xco
core_fft64_flist.txt
core_fft64_
fq_divider.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
alarm_clock.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
serialport.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
digital_clk.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
a8255.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
hw4.epr
"D:\VHDL_EXERCISE\Active_hdl\homework\hw4\src\pcm.vhd" hw4 1 0 7216012
"D:\VHDL_EXERCISE\Active_hdl\homework\hw4\src\test_pcm.vhd" hw4 1 0 0
. . 0 0 0