代码搜索结果

reg4.vhd，reg4_1.vhd,reg8.vhd,add4.gdf,add8.gdf 流水线加法器 mul_8.vhd，mul8.gdf 流水线乘法器 first.vhd,second.vhd 寄存器VHDL优化编码

AR shift_rotate low_level_definition E:/PLD_Courses/2005-2/PicoBlaze/picoblaze/demo_test/../vhdl/shift_rotate.vhd sub00/vhpl07 AR program_counter low_level_definition E:/PLD_Courses/2005-2/PicoBlaze/

V1 76 FL E:/PLD_Courses/2005-2/PicoBlaze/picoblaze/demo_test/../vhdl/stack_ram.vhd 2005/11/11.03:48:41 EN work/STACK_RAM \ FL E:/PLD_Courses/2005-2/PicoBlaze/picoblaze/demo_test/../vhdl/stack

/* $Id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright

/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2

[Library] others = $MODEL_TECH/../modelsim.ini proasic3 = C:/Libero/Designer/lib/modelsim/precompiled/vhdl/proasic3 syncad_vhdl_lib = C:\Libero\Designer/lib/actel/syncad_vhdl_lib presynth = pres

vhdl iputils "D:\work\eccGen256byte\tmp\_cg\_bbx\iputils\iputils_conv.vhd" vhdl iputils "D:\work\eccGen256byte\tmp\_cg\_bbx\iputils\iputils_math.vhd" vhdl iputils "D:\work\eccGen256byte\tmp\_cg\_bbx

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

/////////////////////////////////////////////////////////////////////// // Generate VHDL Source Code // ////////////////////////////////////////////////////////