代码搜索结果
找到约 10,000 项符合
VHDL 的代码
alu.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
proj.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
proj.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
a8251.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
ddr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000
#add_file opti
sdram_vhd_134.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT sdram_vhd_134
DESIGN sdram_vhd_134
DEVFAM virtex
DEVFAMTIME 0
DEVICE xcv300
DEVICETIME 1016218053
DEVPKG bg432
DEVPKGTIME 1016218053
DEV
entries.extra
/bram_block_a.vhdl////
/bram_block_b.vhdl////
/counter2bit.vhdl////
/folded_register.vhdl////
/io_interface.vhdl////
/key_scheduler.vhdl////
/mini_aes.vhdl////
/mix_column.vhdl////
/xtime.vhdl