a8251.qsf

8251的完整的功能的实现,可以进行编译,综合.

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		A8251_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:43:46  AUGUST 29, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE addr_latch.vhd
set_global_assignment -name VHDL_FILE data_latch.vhd
set_global_assignment -name VHDL_FILE dout_mux.vhd
set_global_assignment -name VHDL_FILE Proc.vhd
set_global_assignment -name VHDL_FILE Proc_cmd_reg.vhd
set_global_assignment -name VHDL_FILE PROC_DEC.VHD
set_global_assignment -name VHDL_FILE Proc_mode_reg.vhd
set_global_assignment -name VHDL_FILE Proc_sm.vhd
set_global_assignment -name VHDL_FILE Proc_sync_reg.vhd
set_global_assignment -name VHDL_FILE Rx.vhd
set_global_assignment -name VHDL_FILE Rx_break_cnt.vhd
set_global_assignment -name VHDL_FILE Rx_cntrl.vhd
set_global_assignment -name VHDL_FILE Rx_cntrl_cnt.vhd
set_global_assignment -name VHDL_FILE Rx_cntrl_sm.vhd
set_global_assignment -name VHDL_FILE Rx_data_cnt.vhd
set_global_assignment -name VHDL_FILE Rx_data_reg.vhd
set_global_assignment -name VHDL_FILE Rx_det_cntrl.vhd
set_global_assignment -name VHDL_FILE Rx_error_reg.vhd
set_global_assignment -name VHDL_FILE Rx_par_tree.vhd
set_global_assignment -name VHDL_FILE Rx_ready_reg.vhd
set_global_assignment -name VHDL_FILE Rx_shift_reg.vhd
set_global_assignment -name VHDL_FILE Rx_sync_comp.vhd
set_global_assignment -name VHDL_FILE Rx_sync_stat.vhd
set_global_assignment -name VHDL_FILE Tx.vhd
set_global_assignment -name VHDL_FILE Tx_clk_div.vhd
set_global_assignment -name VHDL_FILE Tx_cntrl.vhd
set_global_assignment -name VHDL_FILE Tx_data_cnt.vhd
set_global_assignment -name VHDL_FILE Tx_data_mux.vhd
set_global_assignment -name VHDL_FILE Tx_fifo.vhd
set_global_assignment -name VHDL_FILE Tx_line_mux.vhd
set_global_assignment -name VHDL_FILE Tx_par_gen.vhd
set_global_assignment -name VHDL_FILE Tx_shift_reg.vhd
set_global_assignment -name VHDL_FILE Tx_state_mach.vhd
set_global_assignment -name VHDL_FILE Tx_status_reg.vhd
set_global_assignment -name VHDL_FILE wr_ext.vhd
set_global_assignment -name VHDL_FILE wr_sync.vhd
set_global_assignment -name VHDL_FILE A8251.vhd

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<NONE>"
set_global_assignment -name FAMILY Stratix
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY A8251

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S25F780C6
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<NONE>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF