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[Files List] d:\Program Files\Aldec\Active-HDL 4.2\VLIB\STD\src\standard.vhd=S d:\Program Files\Aldec\Active-HDL 4.2\VLIB\IEEE\src\stdlogic.vhd=S D:\VHDL_EXERCISE\Active_hdl\homework\hw4\src\pcm.vh

[Files List] d:\Program Files\Aldec\Active-HDL 4.2\VLIB\STD\src\standard.vhd=S d:\Program Files\Aldec\Active-HDL 4.2\VLIB\IEEE\src\stdlogic.vhd=S D:\VHDL_EXERCISE\Active_hdl\homework\hw3\src\hw3.vh

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file D:\VHDL_EXERCISE\counter10\counter10.prd #-- Written on Tue Nov 01 20:53:40 2005 # ### Watch Implementation type ### # watch

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file D:\VHDL_EXERCISE\project1\proj_1.prd #-- Written on Mon Oct 31 12:48:28 2005 # ### Watch Implementation type ### # watch_imp

# # # # Created by Synplify VHDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Tue Nov 01 1

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu