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manchesterdeencoder.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
readme.txt
EP1C12的GWADDA板A口/B口基于DDS的正弦波移相信号发生器（直接VHDL设计）
1、打开GW48PK2系统的电源，
注意打开系统的+/-12V电源开关（在系统左上侧），
2、将GW48系统左下角的拨码开关的“4”向下拨，其余向上。
3、用QuartusII下载2中的DDS_VHDL.SOF，到EP1C12-Q240c8
manchesterdeencoder.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
songer.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
my_sram.vhdsim_par
my_sram.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: Generic_VHDL
my_sram.vhdsim_xlate
my_sram.vhdsim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_VHDL
clock_my.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
mc8051_core.prj
#-- Synplicity, Inc.
#-- Version 6.2.4
#-- Project file mc8051_core.prj
#-- Written on Fri Aug 24 19:26:03 2001
#add_file options
add_file -vhdl -lib work "../vhdl/mc8051_p.vhd"
add_file -vhdl -lib
mc8051_core.prj
#-- Synplicity, Inc.
#-- Version 6.2.4
#-- Project file mc8051_core.prj
#-- Written on Fri Aug 24 19:26:03 2001
#add_file options
add_file -vhdl -lib work "../vhdl/mc8051_p.vhd"
add_file -vhdl -lib
tennis.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu