clock_my.map.qmsg

实光电码盘的输出数据的四倍频

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 13 16:19:55 2006 " "Info: Processing started: Tue Jun 13 16:19:55 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off CLOCK_MY -c CLOCK_MY " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CLOCK_MY -c CLOCK_MY" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLOCK_MY.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLOCK_MY.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLOCK_MY-CLOCK_MY_1 " "Info: Found design unit 1: CLOCK_MY-CLOCK_MY_1" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 23 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CLOCK_MY " "Info: Found entity 1: CLOCK_MY" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLR CLOCK_MY.vhd(36) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(36): signal \"CLR\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_OE CLOCK_MY.vhd(40) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(40): signal \"READ_OE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(41) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(41): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(42) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(42): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(43) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(43): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(44) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(44): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 44 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(45) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(45): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(46) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(46): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 46 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "READ_ADD CLOCK_MY.vhd(47) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(47): signal \"READ_ADD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER CLOCK_MY.vhd(48) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(48): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DATA_OUT CLOCK_MY.vhd(34) " "Warning: VHDL Process Statement warning at CLOCK_MY.vhd(34): signal or variable \"DATA_OUT\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DATA_OUT\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "CLOCK_MY.vhd" "" { Text "E:/altera/quartus42/my_vhdl/zhuangtai/CLOCK_MY.vhd" 34 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "61 " "Info: Ignored 61 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "61 " "Info: Ignored 61 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "158 " "Info: Implemented 158 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "127 " "Info: Implemented 127 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "16 " "Info: Implemented 16 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 16:20:30 2006 " "Info: Processing ended: Tue Jun 13 16:20:30 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:36 " "Info: Elapsed time: 00:00:36" {  } {  } 0}  } {  } 0}