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V1 42 FL E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl 2007/04/06.23:01:00 FL E:/VHDL/waitpast/dianzheng/dianzheng.vhf 2007/04/06.23:06:14 FL E:/zsx/dianzheng/colour_control.vhdl 2007/04/11.12:26:32 EN w

sch2vhdl -family spartan2 -flat -suppress -w JT.sch jt.vhf xst -intstyle ise -ifn __projnav/jt.xst -ofn jt.syr ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ.ucf -p xc2s50-tq144-6 jt.ngc j

/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2

Release 5.1i - xst F.23 Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to . CPU : 0.00 / 0.37 s | Elapsed : 0.00 / 1.00 s --> ==================================

Project Information d:\source\aaaaaa\sourcecode\cpld\d_trig_vhdl\dffe_v.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 12/13/2005 23:20:43 Copyright (C) 1988-2002 Al

Project Information d:\source\aaaaaa\sourcecode\cpld\t_trig_vhdl\tffe_v.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 12/13/2005 23:26:57 Copyright (C) 1988-2002 Al

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE