hdpdeps.ref

8*8点阵的实现

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FL E:/VHDL/waitpast/dianzheng/fpq2ms.vhdl 2007/04/06.23:01:00
FL E:/VHDL/waitpast/dianzheng/dianzheng.vhf 2007/04/06.23:06:14
FL E:/zsx/dianzheng/colour_control.vhdl 2007/04/11.12:26:32
EN work/HONG_LV         FL E:/zsx/dianzheng/colour_control.vhdl \
      PB ieee/STD_LOGIC_1164
AR work/HONG_LV/HONG_LV_ARCH FL E:/zsx/dianzheng/colour_control.vhdl \
      EN work/HONG_LV
FL e:/vhdl/dianzheng/fpq10ms.vhdl 2007/03/19.17:18:50
FL E:/zsx/dianzheng/lie_scan.vhdl 2007/04/06.22:50:34
EN work/DZ_SCAN         FL E:/zsx/dianzheng/lie_scan.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_UNSIGNED PB ieee/STD_LOGIC_ARITH
AR work/DZ_SCAN/DZ_SCAN_ARCH FL E:/zsx/dianzheng/lie_scan.vhdl EN work/DZ_SCAN
FL E:/VHDL/waitpast/dianzheng/chw.vhdl 2007/03/19.16:56:42
FL e:/vhdl/dianzheng/cnta.vhdl 2007/03/19.17:20:58
FL E:/VHDL/waitpast/dianzheng/colour_control.vhdl 2007/04/06.22:54:08
FL E:/VHDL/waitpast/dianzheng/cnta.vhdl 2007/03/19.17:20:58
FL e:/vhdl/dianzheng/cont.vhdl 2007/03/19.17:13:48
FL E:/VHDL/waitpast/dianzheng/cont.vhdl 2007/03/19.17:13:48
FL E:/zsx/dianzheng/chw.vhdl 2007/04/11.12:19:56
EN work/CHW             FL E:/zsx/dianzheng/chw.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CHW/BEHAVIORAL  FL E:/zsx/dianzheng/chw.vhdl EN work/CHW
FL E:/zsx/dianzheng/dianzheng.vhf 2007/04/11.12:28:00
EN work/DIANZHENG       FL E:/zsx/dianzheng/dianzheng.vhf PB ieee/STD_LOGIC_1164 \
      PH ieee/NUMERIC_STD
AR work/DIANZHENG/BEHAVIORAL FL E:/zsx/dianzheng/dianzheng.vhf EN work/DIANZHENG \
      CP CHW            CP CNTA           CP CONT           CP DZ_SCAN        CP HONG_LV \
      CP FPQ2MS
FL E:/zsx/dianzheng/cnta.vhdl 2007/03/19.17:20:58
EN work/CNTA            FL E:/zsx/dianzheng/cnta.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CNTA/BEHAVIORAL FL E:/zsx/dianzheng/cnta.vhdl EN work/CNTA
FL E:/zsx/dianzheng/cont.vhdl 2007/04/11.12:27:44
EN work/CONT            FL E:/zsx/dianzheng/cont.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CONT/BEHAVIORAL FL E:/zsx/dianzheng/cont.vhdl EN work/CONT
FL e:/vhdl/dianzheng/chw.vhdl 2007/03/19.16:56:42
FL E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl 2007/03/19.17:18:50
EN work/FPQ10MS         FL E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FPQ10MS/BEHAVIORAL FL E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl \
      EN work/FPQ10MS
FL E:/zsx/dianzheng/fpq2ms.vhdl 2007/04/06.23:01:00
EN work/FPQ2MS          FL E:/zsx/dianzheng/fpq2ms.vhdl PB ieee/STD_LOGIC_1164 \
      PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/FPQ2MS/BEHAVIORAL FL E:/zsx/dianzheng/fpq2ms.vhdl EN work/FPQ2MS
FL E:/VHDL/waitpast/dianzheng/lie_scan.vhdl 2007/04/06.22:50:34
FL e:/vhdl/dianzheng/dianzheng.vhf 2007/03/19.17:22:58