代码搜索结果

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

JDF G // Created by Project Navigator ver 1.0 PROJECT Untitled DESIGN gold_code_vhd_217 DEVFAM virtex DEVFAMTIME 1016217548 DEVICE xcv300 DEVICETIME 1016217548 DEVPKG bg432 DEVPKGTIME 1016217

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu

# Schematic : PDCL (jhdparse) __projnav/jsq_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/pingche_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp kzq.spl __projnav

sch2vhdl -family spartan2 -flat -suppress -w jsq.sch jsq.vhf xst -intstyle ise -ifn __projnav/jsq.xst -ofn jsq.syr

JDF G // Created by Project Navigator ver 1.0 PROJECT qiangdaqi4ren DESIGN qiangdaqi4ren DEVFAM spartan2 DEVFAMTIME 0 DEVICE xc2s50 DEVICETIME 0 DEVPKG tq144 DEVPKGTIME 0 DEVSPEED -6 DEVSPE

sch2vhdl -family spartan2 -flat -suppress -w qd.sch qd.vhf xst -intstyle ise -ifn __projnav/qd.xst -ofn qd.syr ngdbuild -intstyle ise -dd e:\qiangdaqi4ren/_ngo -uc yj3.ucf -p xc2s50-tq144-6 qd.ngc