gold_code_vhd_217.npl

来自「gold_code_vhd_217源程序」· NPL 代码 · 共 30 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT Untitled
DESIGN gold_code_vhd_217
DEVFAM virtex
DEVFAMTIME 1016217548
DEVICE xcv300
DEVICETIME 1016217548
DEVPKG bg432
DEVPKGTIME 1016217548
DEVSPEED -6
DEVSPEEDTIME 1016217548
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
DOCUMENT readme
STIMULUS gold_code_tb.vhd
SOURCE vhd_top.vhd
SOURCE vhd_suba.vhd
SOURCE vhd_subb.vhd
[Normal]
p_ModelSimSimRunTime_tb=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1054568366, 5000ns
[STRATEGY-LIST]
Normal=True