代码搜索结果

[Library] others = $MODEL_TECH/../modelsim.ini fusion = $MODEL_TECH/../actel/vlog/fusion syncad_vhdl_lib = C:\Libero8.1\Designer/lib/actel/syncad_vhdl_lib [vcom] VHDL93 = 1 [vsim]

[Library] others = $MODEL_TECH/../modelsim.ini fusion = $MODEL_TECH/../actel/vlog/fusion syncad_vhdl_lib = C:\Libero8.1\Designer/lib/actel/syncad_vhdl_lib [vcom] VHDL93 = 1 [vsim] I

----------------------------------------------------------------------- -- -- Original Code Copyright (c) 1999 by Esperan. All rights reserved. -- www.esperan.com -- -- This source file may be

vhdl work "op_sub.vhd" vhdl work "op_mux.vhd" vhdl work "op_add.vhd" vhdl work "alu_module.vhd"

# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga\coregen.log # bu

Log File Links:

sch2vhdl -family spartan2 -flat -suppress -w VGA.sch vga.vhf sch2vhdl -family spartan2 -flat -suppress -w VGA.sch vga.vhf sch2vhdl -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # do microoven_tbw.tdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE