ddrv.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Ddrv.vhd
-- Bit based display driver 
--
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity DDRV is
port (ALARM_TIME, CURRENT_TIME  : in std_logic_vector (3 downto 0);
      SHOW_A                    : in std_logic;
      SOUND_ALARM               : out std_logic;
      DISPLAY                   : out std_logic_vector (6 downto 0));
end DDRV;  

architecture RTL of DDRV is
   
-- constants for the segments to light for each digit 0 to 9
   constant ZERO_SEG  : std_logic_vector(6 downto 0):= "0111111";
   constant ONE_SEG   : std_logic_vector(6 downto 0):= "0000110";
   constant TWO_SEG   : std_logic_vector(6 downto 0):= "1011011";
   constant THREE_SEG : std_logic_vector(6 downto 0):= "1001110";
   constant FOUR_SEG  : std_logic_vector(6 downto 0):= "1100110";
   constant FIVE_SEG  : std_logic_vector(6 downto 0):= "1101101";
   constant SIX_SEG   : std_logic_vector(6 downto 0):= "1111101";
   constant SEVEN_SEG : std_logic_vector(6 downto 0):= "0000111";
   constant EIGHT_SEG : std_logic_vector(6 downto 0):= "1111111";
   constant NINE_SEG  : std_logic_vector(6 downto 0):= "1101111";
   
begin

  --  PUT VHDL CODE HERE!

end RTL ;