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analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ctr.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_dec.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_rom.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_alu.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pvl_resolve OL;C;6.2b;35 31 b1 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/verilog/vlresolve.vhd l0 L9 V?GckcDU8_EkiBze