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# Bencher : Creating project file test_tb_bencher.prj # ProjNav -> New Source -> TBW test_tb.vhw test_tb.ano test_tb.tfw test_tb.ant # Bencher : Creating project file clk_tb_bencher.prj # Pro

change_names -rules vhdl define_name_rules lowercase -restricted "a-z" -type cell change_names -rules lowercase

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni