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100vhdl+
--这是子类型和部件声明的包
--用于区分向量类型的不同宽度
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
PACKAGE pkg_types IS
SUBTYPE bit1 IS std_ulogic;
SUBTYPE bit
100vhdl+
entity decoder is
port( I0 : in Bit;
I1 : in Bit;
O0 : out Bit;
O1 : out Bit;
O2 : out Bit;
O3 : out Bit);
end entity;
architecture decoder_archi of decoder is
signal
100vhdl+
--Page :291,292
--Objective :Transport driver preemption
--Filename :test_113.vhd
--Author :Joseph Pick
entity Test_113 is
end Test_113;
architecture Behave
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--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
100vhdl+
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
100vhdl+
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- I
100vhdl+
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distribu
100vhdl+
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book