100vhdl+

100vhdl例子

entity decoder is
	port( I0 : in Bit;
		  I1 : in Bit;
		  O0 : out Bit;
		  O1 : out Bit;
		  O2 : out Bit;
		  O3 : out Bit);
end entity;

architecture decoder_archi of decoder is
	signal clk : bit := '0';
begin
--	dec:	
--	process ( clk )
--	variable input: bit_vector(0 to 1);
--	begin
--		input := I0 & I1;
--		case (input) is
--			when "00" => O0 <= '1'; O1 <= '0'; O2 <= '0'; O3 <= '0';
--			when "01" => O0 <= '0'; O1 <= '1'; O2 <= '0'; O3 <= '0';
--			when "10" => O0 <= '0'; O1 <= '0'; O2 <= '1'; O3 <= '0';
--			when "11" => O0 <= '0'; O1 <= '0'; O2 <= '0'; O3 <= '1';
--			when OTHERS => NULL; 
--		end case;
--	end process;
	O0 <= '1' when I0 = '0' and I1 = '0' else
		  '0';
	O1 <= '1' when I0 = '0' and I1 = '1' else
		  '0';
	O2 <= '1' when I0 = '1' and I1 = '0' else
		  '0';
	O3 <= '1' when I0 = '1' and I1 = '1' else
		  '0';
		
	clk <= not clk after 10 ns;
end;

entity bench is
end entity;

architecture bench_archi of bench is
	component d
		port( I0 : in Bit;
			  I1 : in Bit;
			  O0 : out Bit;
			  O1 : out Bit;
			  O2 : out Bit;
			  O3 : out Bit);
	end component;
	signal t_i : bit_vector(0 to 1) := "00";
	signal t_o : bit_vector(0 to 3) := "0000";
for u1: d use entity work.decoder(decoder_archi);
begin
	u1: d
		port map( t_i(0), 
				 t_i(1),
				 t_o(0),
				 t_o(1),
				 t_o(2),
				 t_o(3) );
	process
	begin
		t_i <=  "01" after 10 ns,
				"10" after 20 ns,
				"11" after 30 ns,
				"00" after 40 ns,
				"11" after 50 ns;
		wait for 100 ns;
		assert false
		report "End of simulation"
		severity failure;
	end process;
end;