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找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/397462/8049097

qmsg iic.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/397462/8049853

qmsg serialport.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/396354/8111201

rpt digital_clk.map.rpt

Analysis & Synthesis report for digital_clk Thu Dec 25 14:27:17 2008 Version 4.0 Build 190 1/28/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Le
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www.eeworm.com/read/396350/8113237

qmsg prev_cmp_cnt_fry.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
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www.eeworm.com/read/296020/8128526

txt readme.txt

adc_interface.zip This zip file contains the following source code. VHDL SOURCE CODE: ----------------- top_level.vhd -- Top level VHDL file + adc_interface.vhd -- State machin
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www.eeworm.com/read/246855/12700687

npl 8051_interface.npl

JDF F // Created by Project Navigator ver 1.0 PROJECT Untitled DESIGN 8051_interface Normal DEVFAM xpla3 DEVFAMTIME 315558000 DEVICE xcr3064xl DEVICETIME 315558000 DEVPKG VQ100 DEVPKGTIME 315
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www.eeworm.com/read/246303/12738587

qmsg ledwater.tan.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
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www.eeworm.com/read/246301/12738723

qmsg key0.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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www.eeworm.com/read/331968/12790128

qsf fir.qsf

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth
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www.eeworm.com/read/143966/12826498

ini modelsim.ini

[Library] others = $MODEL_TECH/../modelsim.ini apa = $MODEL_TECH/../actel/vhdl/apa syncad_lib = C:\Libero\Designer/lib/actel/syncad_lib [vcom] VHDL93 = 1
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