serialport.map.qmsg

VHDL基础的编程源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 25 21:22:51 2007 " "Info: Processing started: Sun Mar 25 21:22:51 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serialport -c serialport" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file baud_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 baud_div-baud_div_architecture " "Info: Found design unit 1: baud_div-baud_div_architecture" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 baud_div " "Info: Found entity 1: baud_div" {  } { { "baud_div.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/baud_div.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "charlib8_8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file charlib8_8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 charlib8_8-charlib8_8_architecture " "Info: Found design unit 1: charlib8_8-charlib8_8_architecture" {  } { { "charlib8_8.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/charlib8_8.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 charlib8_8 " "Info: Found entity 1: charlib8_8" {  } { { "charlib8_8.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/charlib8_8.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/counter.vhd" 34 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledarray_drv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ledarray_drv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ledarray_drv-ledarray_drv_architecture " "Info: Found design unit 1: ledarray_drv-ledarray_drv_architecture" {  } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 60 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ledarray_drv " "Info: Found entity 1: ledarray_drv" {  } { { "ledarray_drv.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/ledarray_drv.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialport_rx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serialport_rx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serialport_rx-serialport_rx_architecture " "Info: Found design unit 1: serialport_rx-serialport_rx_architecture" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serialport_rx " "Info: Found entity 1: serialport_rx" {  } { { "serialport_rx.vhd" "" { Text "H:/03-源码文件/VHDL/08-串口接收/serialport_rx.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialport.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file serialport.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 serialport " "Info: Found entity 1: serialport" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serialport " "Info: Elaborating entity \"serialport\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst " "Warning: Port \"carrier\" of type counter and instance \"inst\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 312 424 -376 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "baudrate_clock baud_div inst3 " "Warning: Port \"baudrate_clock\" of type baud_div and instance \"inst3\" is missing source signal" {  } { { "serialport.bdf" "" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -104 312 512 -8 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ledarray_drv ledarray_drv:inst2 " "Info: Elaborating entity \"ledarray_drv\" for hierarchy \"ledarray_drv:inst2\"" {  } { { "serialport.bdf" "inst2" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 880 1056 -248 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst\"" {  } { { "serialport.bdf" "inst" { Schematic "H:/03-源码文件/VHDL/08-串口接收/serialport.bdf" { { -472 312 424 -376 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}