代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/375322/9364118
tlg ddr_sdram.tlg
Synthesizing work.ddr_sdram.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":131:14:131:16|Port direction mismatch between component and entity
Synthesizing work.pll1.s
www.eeworm.com/read/374298/9411939
qmsg dzxs.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
www.eeworm.com/read/177213/9464737
npl clk_div3.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT clk_div3
DESIGN clk_div3
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s150
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
www.eeworm.com/read/174927/9568245
npl dpram2.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT dpram2
DESIGN dpram2
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
D
www.eeworm.com/read/174896/9570422
vhd e10281_obf.vhd
---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool
www.eeworm.com/read/170129/9818113
gfl lab2.gfl
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
addsub_addsubtest_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : S
www.eeworm.com/read/169299/9868324
cfg compxlib.cfg
#**************************************************************
# compxlib initialization file, compxlib Release 6.1i *
# File Name :- compxlib.cfg *
#
www.eeworm.com/read/169299/9868346
vhdsim_par dq024.vhdsim_par
dq024.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: Modelsim_VHDL
www.eeworm.com/read/169299/9868746
vhdsim_par mdecode.vhdsim_par
mdecode.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: Modelsim_VHDL
www.eeworm.com/read/169299/9868759
vhdsim_par sel4_1.vhdsim_par
sel4_1.vhdsim_par -- generated only for ProjNav status tracking
Simulation Model Target: Modelsim_VHDL