clk_div3.npl

vhdl语言写的基数分频器

JDF G
// Created by Project Navigator ver 1.0
PROJECT clk_div3
DESIGN clk_div3
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s150
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 1142232133
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE clk_div3.vhd
STIMULUS clk_div3_tbw.tbw
[STRATEGY-LIST]
Normal=True