代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/443859/7621579

npl vga.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT vga DESIGN vga DEVFAM spartan2e DEVFAMTIME 0 DEVICE xc2s300e DEVICETIME 0 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -6 DEVSPEEDTIME 0 DEVTOPL
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www.eeworm.com/read/440800/7681075

qmsg video.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
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www.eeworm.com/read/435556/7790440

qsf time_lock.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
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www.eeworm.com/read/199789/7822534

txt readme.txt

注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
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www.eeworm.com/read/398865/7914191

npl vga.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT vga DESIGN vga DEVFAM spartan2e DEVFAMTIME 0 DEVICE xc2s300e DEVICETIME 0 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -6 DEVSPEEDTIME 0 DEVTOPL
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www.eeworm.com/read/433577/7921435

qsf szsz.qsf

# Copyright (C) 1991-2008 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/433506/7925380

cdf color.cdf

/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EP1C3T144) Path("E:/EDA_VHDL_Expt3/Ch
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www.eeworm.com/read/433506/7925411

rpt color.asm.rpt

Assembler report for COLOR Tue May 10 15:13:25 2005 Version 4.1 Build 181 06/29/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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www.eeworm.com/read/198238/7946257

txt readme.txt

注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
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www.eeworm.com/read/397615/8032728

qmsg dac.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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