dac.map.qmsg

利用EDA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 23 15:28:55 2007 " "Info: Processing started: Fri Mar 23 15:28:55 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DAC -c DAC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DAC -c DAC" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DAC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DAC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DAC-DAC " "Info: Found design unit 1: DAC-DAC" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DAC " "Info: Found entity 1: DAC" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DAC " "Info: Elaborating entity \"DAC\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "nRESET DAC.vhd(35) " "Warning: VHDL Process Statement warning at DAC.vhd(35): signal \"nRESET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DBUS DAC.vhd(88) " "Warning: VHDL Process Statement warning at DAC.vhd(88): signal \"DBUS\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 88 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(106) " "Warning: VHDL Process Statement warning at DAC.vhd(106): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 106 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(108) " "Warning: VHDL Process Statement warning at DAC.vhd(108): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 108 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(110) " "Warning: VHDL Process Statement warning at DAC.vhd(110): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(112) " "Warning: VHDL Process Statement warning at DAC.vhd(112): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 112 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(114) " "Warning: VHDL Process Statement warning at DAC.vhd(114): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(116) " "Warning: VHDL Process Statement warning at DAC.vhd(116): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(118) " "Warning: VHDL Process Statement warning at DAC.vhd(118): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(120) " "Warning: VHDL Process Statement warning at DAC.vhd(120): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 120 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(122) " "Warning: VHDL Process Statement warning at DAC.vhd(122): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 122 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS1 DAC.vhd(156) " "Warning: VHDL Process Statement warning at DAC.vhd(156): signal \"CS1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 156 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD1 DAC.vhd(157) " "Warning: VHDL Process Statement warning at DAC.vhd(157): signal \"RD1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 157 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR1 DAC.vhd(158) " "Warning: VHDL Process Statement warning at DAC.vhd(158): signal \"WR1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 158 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "P131 DAC.vhd(159) " "Warning: VHDL Process Statement warning at DAC.vhd(159): signal \"P131\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DBUS DAC.vhd(33) " "Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable \"DBUS\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DBUS\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "AD_VALUE DAC.vhd(33) " "Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable \"AD_VALUE\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"AD_VALUE\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ledcs DAC.vhd(33) " "Warning: VHDL Process Statement warning at DAC.vhd(33): signal or variable \"ledcs\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ledcs\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ledcs\$latch " "Warning: Latch ledcs\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA reduce_nor~11 " "Warning: Ports D and ENA on the latch are fed by the same signal reduce_nor~11" {  } {  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[0\]\$latch " "Warning: Latch DBUS\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "process1_566 " "Warning: Latch process1_566 has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA STATUS\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal STATUS\[1\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0} { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[1\]\$latch " "Warning: Latch DBUS\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[2\]\$latch " "Warning: Latch DBUS\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[3\]\$latch " "Warning: Latch DBUS\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[4\]\$latch " "Warning: Latch DBUS\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[5\]\$latch " "Warning: Latch DBUS\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[6\]\$latch " "Warning: Latch DBUS\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "DBUS\[7\]\$latch " "Warning: Latch DBUS\[7\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "ENA CLR STATUS\[3\] " "Warning: Ports ENA and CLR on the latch are fed by the same signal STATUS\[3\]" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 17 -1 0 } }  } 0}  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "RAMCS VCC " "Warning: Pin \"RAMCS\" stuck at VCC" {  } { { "DAC.vhd" "" { Text "D:/sopc/advanced/DAC/DAC.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "63 " "Info: Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "47 " "Info: Implemented 47 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 41 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 23 15:28:59 2007 " "Info: Processing ended: Fri Mar 23 15:28:59 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}