代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/158843/10724431

adf cordic_beh.adf

[Project] Current Flow=Multivendor VCS=0 version=1 Current Config=compile [Configurations] compile=cordic_beh [Library] cordic_beh=.\cordic_beh.lib [$LibMap$] cordic_beh=. Active_lib=
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www.eeworm.com/read/350244/10755192

qsf vpc.qsf

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/349305/10836984

qmsg sramtest.fnsim.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
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www.eeworm.com/read/274663/10860320

nlf xccpld_timesim.nlf

Release 7.1i - netgen H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim xccpld.nga xccpld_timesim.vhd Readin
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www.eeworm.com/read/274663/10860331

par_nlf xccpld.par_nlf

Release 7.1i - netgen H.38 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim xccpld.nga xccpld_timesim.vhd Readin
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www.eeworm.com/read/419416/10869579

prj fifo12bit_2k.prj

vhdl work "data_part.vhd" vhdl work "data_unite.vhd" vhdl work "fifo12bit_2k.vhf"
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www.eeworm.com/read/273857/10898031

qsf timer.qsf

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/417160/11001828

log reg10.log

==================================================== = vvToForm v0.1 VHDL to Verilog RTL transformer = Release: Brier EDA Studio = *** All Rights Reserved By Brier Van **** ======================
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www.eeworm.com/read/270524/11034172

qsf wash.qsf

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu
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www.eeworm.com/read/151712/6959604

txt readme.txt

注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
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