代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/154101/5642029
prj i2c.prj
vhdl work ../../source/upcnt4.vhd
vhdl work ../../source/shift.vhd
vhdl work ../../source/i2c_control.vhd
vhdl work ../../source/uc_interface.vhd
vhdl work ../../source/i2c.vhd
www.eeworm.com/read/154100/5642131
gfl wtut_sc.gfl
# Schematic : View VHDL Functional Model
stopwatch.vhf
stopwatch.cmd_log
# Schematic : View VHDL Functional Model
cnt60.vhf
cnt60.cmd_log
# XAW : View VHDL Source
DCM1.vhd
# Schematic : View V
www.eeworm.com/read/198746/6786444
udo mvbc3tbw.udo
-- ProjNav VHDL simulation template: mvbc3tbw.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/198746/6786484
log coregen.log
# Xilinx CORE Generator 6.1i
# User = 20067144
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\2006\fpga_design\mvbc3\mvbc3\coregen.log
# busformat
www.eeworm.com/read/471480/6894402
rpt count10_v.rpt
Project Information d:\source\aaaaaa\sourcecode\cpld\count_vhdl\count10_v.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/13/2005 23:37:48
Copyright (C) 1988-2002 Al
www.eeworm.com/read/394067/8249949
txt fifo8x16_flist.txt
# Output products list for
FIFO8x16.asy
FIFO8x16.ngc
FIFO8x16.sym
FIFO8x16.v
FIFO8x16.veo
FIFO8x16.vhd
FIFO8x16.vho
FIFO8x16.xco
FIFO8x16_fifo_generator_v3_3_xst_1_vhdl.prj
FIFO8x
www.eeworm.com/read/174463/9586477
cmd_log binarycounter.cmd_log
xst -ise "E:/vhdl/binarycounter/binarycounter" -intstyle ise -ifn BinaryCounter.xst -ofn BinaryCounter.syr
xst -ise "E:/vhdl/binarycounter/binarycounter" -intstyle ise -ifn BinaryCounter.xst -ofn Bin
www.eeworm.com/read/370579/9595089
txt 将16进制转化为std_logic.txt
VHDL: Converting a Hexadecimal Value to a Standard Logic Vector
This example shows how to convert a hexadecimal value to a std_logic_vector.
It is shown in both VHDL '87 (IEEE Std 1076-1987) and