anal.out

来自「100 VHDL programming examples 100 VHDL p」· OUT 代码 · 共 6 行

OUT
6
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E:/vhdl_tools/100Examples/2_ADDER/2_ADDER.VHD:
	  pout <= in1+in2 after 2 ns;

	             ^
**Error: E:/vhdl_tools/100Examples/2_ADDER/2_ADDER.VHD  line 13
	Type mismatch on left and/or right operand of binary operator. (VSS-523)

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