代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/139685/13139829

txt convert.txt

VHDL: Converting a Hexadecimal Value to a Standard Logic Vector This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and
·
www.eeworm.com/read/316453/13522430

txt readme.txt

请注意: 第94例是SPARC芯片的源描述,在本书的光盘中没有给出其源描述 代码,有关该描述的框架请参考. 如果您需要有关SPARC的详细资料以及完整代码,请与北京理工大学 ASIC研究所联系. 联系方法: 电话:010-68912434 信函:北京理工大学ASIC研究所 刘明业 教授收 邮编:100081
·
www.eeworm.com/read/316426/13522890

udo fin.udo

-- ProjNav VHDL simulation template: fin.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
·
www.eeworm.com/read/316426/13522895

udo ss.udo

-- ProjNav VHDL simulation template: ss.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
·
www.eeworm.com/read/316426/13522899

udo pp.udo

-- ProjNav VHDL simulation template: pp.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
·
www.eeworm.com/read/316426/13522973

log coregen.log

# Xilinx CORE Generator 6.2i # User = acer Initializing default project... Loading plug-ins... All runtime messages will be recorded in D:\sum\coregen.log # busformat=BusFormatAngleBracketNotRipp
·
www.eeworm.com/read/316203/13528470

txt convert.txt

VHDL: Converting a Hexadecimal Value to a Standard Logic Vector This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and
·
www.eeworm.com/read/314805/13558721

udo cpu_16_wave.udo

-- ProjNav VHDL simulation template: cpu_16_wave.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
·
www.eeworm.com/read/314805/13558852

udo wave.udo

-- ProjNav VHDL simulation template: wave.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
·
www.eeworm.com/read/314805/13558857

gfl mycpu16.gfl

# ProjNav -> New Source -> TBW e:\资料\计算机设计与实践\mycpu16\__projnav\hb_cmds # Bencher Waveform : PDCL (jhdparse) # ModelSim : Simulate Behavioral VHDL Model cpu_16_wave.fdo # ModelSim : Simulate Beha
·