coregen.log

来自「这是一个用VHDL写的简易的CPU的程序」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.2i
# User = acer
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\sum\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\sum
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=D:\sum
SETPROJECT .
Set current Project to D:\sum
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1039
XIPCPJSENDCORES virtex