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VHDL 的代码
fenping.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity fenping is
port(clk:in std_logic;
clks1:out std_logic);
end;
Architect
minute.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity minute1 is
Port(clkm, reset:in std_logic;
--M1:in std_logic_vector(7 downt
yima.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity yima is
Port(sec1,sec2,min1,min2,hou1,hou2: in std_logic_vector(3 downto 0);
hour1.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour1 is
Port(clkh,reset:in std_logic;
--h1:in std_logic_vector(7 downto 0
alm.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity alarm1 is
Port(reset:in std_logic;
Min1,min2:in std_logic_vect
second.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity second1 is
Port(clks, reset:in std_logic;
--S1:in std_logic_vector(7 downt
hour.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour11 is
Port(clkh,reset:in std_logic;
--h1:in std_logic_vector(7 downto
hour11.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
jhgjgh.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
vhdl.fc2
#----------------------------------------------------------
# Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2
# for the book: DSP with FPGAs (2. edition)
# Author-EMAIL: Uwe.Meyer-Baese@